Summary
I am a Senior Design Verification Engineer at Tenstorrent, where I work on test generators, including the open source Riescue suite. Previously at Tenstorrent, I verified the implementation of the hypervisor extension on Ascalon, a high performance out of order superscalar core, including writing tests and architectural coverage and debugging RTL test failures. Before Tenstorrent, I expanded and improved a formal model of the x86 ISA written in the ACL2 theorem prover to allow it to boot Linux and implemented an address translation caching mechanism. I wrote my honors thesis on that work and published a paper in FMCAD.
Education
Bachelor of Science in Computer Science - University of Texas at Austin
Austin, TX • Aug 2022 - Dec 2024 | GPA: 3.9
Honors Thesis:
Booting a Linux Kernel Modified to Minimize Peripheral Requirements on the ACL2 Model of the X86 ISA
Relevant Coursework:
Advanced Computer Architecture
Computer Architecture
Computer Networks
Cryptography
Data Structures
Discrete Math
Honors Operating Systems
Programming for Performance
Theory of Computation
Individual Study Courses: (Supervised by Dr. Warren A. Hunt, Jr.)
Computer Science Honors Thesis
Undergraduate Reading and Research
Work Experience
Tenstorrent
Sr. Engineer, Design Verification — Apr 2026 - Present
Design Verification Engineer — Jan 2025 - Apr 2026
Austin, TX
- Develop test generators including the open source RiESCUE suite and CoreTP. RiescueC and CoreTP will be used to generate many of the official compliance tests for the RISC-V architecture.
- Develop internal core level test generators and a RISC-V page table generator.
- Develop a micro-architecture agnostic memory ordering stimulus generator and checker that require no internal core instrumentation, suitable for use in emulation where instrumentation is expensive, and on any RISC-V core with minimal testbench support.
- Support several internal customers of these test generators and open source users.
- Verified the implementation of the hypervisor feature on Ascalon, a high performance out-of-order superscalar core.
- Wrote architectural coverage, tests, and debugged RTL test failures for the hypervisor feature.
- Found many bugs across the core, our open source instruction set simulator Whisper, and the testbench.
Intel Corporation
Formal Verification Intern — May 2024 - Aug 2024
Austin, TX
- Contributed to the formal model of the x86 ISA written in ACL2.
- Proved theorems in ACL2 regarding the behavior of the model, with a particular focus on address translation using a new TLB (Translation Lookaside Buffer).
- Identified and fixed several bugs in the x86 model.
- Proved the correctness of an x86 program called "zeroCopy," which involved moving data within the virtual address space by modifying page tables.
- Thoroughly documented the changes made to the model, ensuring clarity and ease of understanding for future contributors.
- The work is now publicly available under a BSD style license as part of the ACL2 Community Books.
UT Austin
Undergraduate Research Assistant — May 2023 - Aug 2023
Austin, TX (Remote)
- Supervised by Dr. Warren A. Hunt, Jr.
- Expanded the formal model of the x86 ISA written in ACL2 to make it capable of booting a modified Linux kernel, including modeling timer and TTY peripherals, modeling interrupt and exception behavior, and implementing additional instructions.
- Worked toward being able to prove theorems about arbitrary x86 code using the ACL2 theorem prover.
- Continued work on this project as part of undergraduate research courses and defended an honors thesis on it.
SIC Digital
Full Stack Developer — Oct 2020 - Jul 2022
Austin, TX (Remote)
- Worked on More Pickups, a service used by organizations to manage picking up donated items from donors' homes.
- Designed and implemented a prototype microservice-based backend architecture.
- Worked with JavaScript, Express, and PostgreSQL on the backend and HTML, CSS, JavaScript, and React on the web-based frontend.
- Created a React Native-based cross-platform mobile app.
Freelance Work
Web Developer — Jun 2016 - May 2022
Houston, TX
- Worked on websites built with WordPress and Drupal content management systems.
- Used PHP, HTML, CSS, and JavaScript to add functionality that clients requested.
Publications
A Method for the Verification of Memory Management Software in the Presence of TLBs
Yahya Sohail and Warren Hunt
Formal Methods in Computer-Aided Design (FMCAD) 2025 — Full Paper •
Paper
Mutable Objects with Several Implementations
Matt Kaufmann, Warren A. Hunt, Jr., and Yahya Sohail
ACL2 Workshop 2025 — Extended Abstract •
Paper
Booting a Linux Kernel Modified to Minimize Peripheral Requirements on the ACL2 Model of the X86 ISA
Yahya Sohail
Department of Computer Science, The University of Texas at Austin — Honors Thesis •
Paper
Projects
x86isa - Formal x86 ISA Model in ACL2
Extended x86isa, the most comprehensive formal model of the x86 ISA, which is implemented as an emulator in ACL2. Enhanced it to boot Linux by adding support for peripherals, interrupts, and exception handling. Developed cosimulation tools which use hardware accelerated virtualization via KVM for bug detection, added a TLB implementation for improved performance, and proved theorems about the impact of the TLB on address translation.
Source
|
Documentation
Technologies Used:
ACL2
Emulation
Formal Verification
KVM
Virtualization
x86 Assembly
Point - Location Based Social Network
Point is a social network that allows users to make posts that show to people nearby the location where the post was made for a duration of time. The backend is an API written in Python with Flask and an SQLite database. The client is a mobile app written in Dart with Flutter.
Technologies Used:
Dart
Flask
Flutter
Python
SQLite
libqsim - Quantum Circuit Simulator Library
A library for the simulation of quantum computers written in C++. Supports simulating arbitrary quantum circuits with arbitrary unitary quantum gates. It is GPU accelerated using ArrayFire.
Source
|
Examples
Technologies Used:
ArrayFire
C++
GPU
Quantum Computing
CHIP-8 Emulator
Implementation of a CHIP-8 virtual machine written in C++, with SFML for the graphics and Dear ImGui for the menus, complete with a debugger and disassembler for CHIP-8 programs.
Source
Technologies Used:
C++
Dear ImGui
SFML